CS492305-CL 查看數據表（PDF） - Cirrus Logic

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CS492305-CL

Multi-Channel Digital Audio Decoders

Cirrus Logic 

I2C Start

I2C Stop

SCCLK

SCDIO

AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

I2C Write Functional Timing

I2C Start

I2C Stop

SCCLK

SCDIO

AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 NACK

INTREQ

Note 1

Note 2

I2C Read Functional Timing

Note 3

Note 4

Note 5

Notes: 1. The ACK for the address byte is driven by the CS4923/4/5/6/7/8/9.

2. The ACKs for the data bytes being read from the CS4923/4/5/6/7/8/9 should be driven by the

host.

3. INTREQ is guaranteed to stay low until the rising edge of SCCLK for last bit of the last byte to

be transferred out of the CS4923/4/5/6/7/8/9

4. A NOACK should be sent by the host after the last byte read to indicate the end of the read

cycle.

5. INTREQ is guaranteed to stay high until the next rising edge of SCCLK (for the ACK/NACK

bit) at which point it may go low again if there is new data to be read. The condition of INTREQ

going low at this point should be treated as a new read condition and a new start condition

followed by an address byte should be sent.

Figure 20. I2C Timing

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