CS4926-CL 查看數據表（PDF） - Cirrus Logic
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CS4926-CL Datasheet PDF : 56 Pages
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CS4923/4/5/6/7/8/9
SWITCHING CHARACTERISTICS—DIGITAL AUDIO OUTPUT
(TA = 25 °C; VA, VD = 3.3 V ±5%; measurements performed under static conditions.)
Parameter
Symbol
Min
MCLK period
(Note 24) Tmclk
40
MCLK duty cycle
(Note 24)
40
SCLK period for Master or Slave mode
(Note 25) Tsclk
40
SCLK duty cycle for Master or Slave mode
(Note 25)
45
Master Mode
(Note 25,26)
SCLK delay from MCLK rising edge, MCLK as an input
Tsdmi
SCLK delay from MCLK rising edge, MCLK as an output
Tsdmo
–5
LRCLK delay from SCLK transition
(Note 27) Tlrds
AUDATA2–0 delay from SCLK transition
(Note 27) Tadsm
Slave Mode
(Note 28)
Time from active edge of SCLKN1(2) to LRCLKN1(2) transition
Tstlr
10
Time from LRCLKN1(2) transition to SCLKN1(2) active edge
Tlrts
10
AUDATA2–0 delay from SCLK transition
(Note 27,29) Tadss
Max
Unit
-
ns
60
%
-
ns
55
%
15
ns
10
ns
10
ns
10
ns
-
ns
-
ns
15
ns
Notes: 24. MCLK can be an input or an output. These specifications apply for both cases.
25. Master mode timing specifications are characterized, not production tested.
26. Master mode is defined as the CS4923 driving both SCLK and LRCLK. When MCLK is an input, it is
divided to produce SCLK and LRCLK.
27. This timing parameter is defined from the non-active edge of SCLK. The active edge of SCLK is the
point at which the data is valid.
28. Slave mode is defined as SCLK and LRCLK being driven by an external source.
29. This specification is characterized, not production tested.
18
DS262F2
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