CS4922-CL 查看數據表（PDF） - Cirrus Logic

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CS4922-CL

MPEG/G.729A Audio Decoder System

Cirrus Logic 

CS4922

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (TA = 25 °C; VA+, VD+ =

5V; Inputs: Logic 0 = GND, Logic 1 = VD+; CL = 20 pF)

Parameter

Symbol Min Typ Max Units

SCLK Frequency

-

- 12.5 MHz

SCLK Pulse Width Low

SCLK Pulse Width High

SCLK rising to FSYNC edge delay

SCLK rising to FSYNC edge setup

SDATA valid to SCLK rising setup

SCLK rising to SDATA hold time

Rise time of SCLK

tsckl

25

-

-

ns

tsckh

25

-

-

ns

(Note 15) tsfds

20

-

-

ns

(Note 15) tsfs

20

-

-

ns

(Note 15) tsss

20

-

-

ns

(Note 15) tssh

20

-

-

ns

tsclr

-

-

20

ns

Notes: 15. The table above assumes data is output on the falling edge and latched on the rising edge. The SCLK

edge is selectable in setting the EDG bit in the ASICN register. The diagram is for EDG = 1.

FSYNC

SCLK

SDATA

t sfds

t sfs

t sckl t sckh

t sclr

t sss t ssh

Figure 4. Serial Audio Port Timing

12

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