CS4525(2008) 查看數據表（PDF） - Cirrus Logic

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CS4525
(Rev.:2008)

30 W Digital Audio Amplifier with Integrated ADC

Cirrus Logic 

9.3.5

CS4525

Aux Serial Port Left Channel Data Select (LChDSel[1:0])

Default = 00

Function:

Selects the data to be sent over the left channel of the auxiliary port serial data output signal.

LChDSel[1:0] Setting Aux Serial Port Left Channel Output Data Source

00 ........................................Channel A.

01 ........................................Channel B.

10 ........................................Sub Channel.

11.........................................Channel B crossover low-pass output.

9.4 Output Configuration (Address 04h)

7

OutputCfg1

6

OutputCfg0

5

PWMDSel1

4

PWMDSel0

3

OutputDly3

2

OutputDly2

1

OutputDly1

0

OutputDly0

9.4.1

Output Configuration (OutputCfg[1:0])

Default = 00

Function:

Identifies the power output configuration. This parameter can only be changed when all modulators and

associated logic are in the power-down state (the PDnAll bit is set). Attempts to write this register while

the PDnAll is cleared will be ignored. See “Output Channel Configurations” on page 45 for more informa-

tion.

OutputCfg[1:0] Setting Power Output Configuration

00 ........................................Channel 1 & 2 Full-Bridge.

01 ........................................Channel 1 & 2 Half-Bridge + Sub Channel Full-Bridge.

10 ........................................Channel 1 Parallel Full-Bridge.

11 ......................................... Reserved.

9.4.2

PWM Signals Output Data Select (PWMDSel[1:0])

Default = 00

Function:

Selects the PWM data output on the PWM_SIG1 and PWM_SIG2 output signals.See “PWM_SIG Logic-

Level Output Configurations” on page 49 for more information.

PWMDSel Setting

PWM Signal Output Mapping

00 ........................................PWM_SIG1 output disabled.

PWM_SIG2 output disabled.

01 ........................................Channel 1 output on PWM_SIG1.

Channel 2 output on PWM_SIG2.

10 ........................................Channel 1 output on PWM_SIG1.

Sub Channel output on PWM_SIG2.

11.........................................Channel 2 output on PWM_SIG1.

Sub Channel output on PWM_SIG2.

9.4.3

Channel Delay Settings (OutputDly[3:0])

Default = 0000

Function:

The channel delay bits allow delay adjustment of each of the power output audio channels. The value of

this register determines the amount of delay inserted in the output path. The delay time is calculated by

multiplying the register value by the period of the SYS_CLK or crystal input clock source. These bits can

DS726PP3

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