CS4525(2008) 查看數據表（PDF） - Cirrus Logic
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CS4525 Datasheet PDF : 98 Pages
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CS4525
6.2.2.2 Power-Down Sequence
1. Bring MUTE low to mute the device’s outputs and minimize audible pops.
2. Bring RST low to halt the operation of the device.
The device’s power consumption will be brought to an absolute minimum.
3. The SYS_CLK signal may now be removed. See section 6.2.1 on page 54 for more information.
4. Remove power.
6.2.3
Input Source Selection
The CS4525 can accept analog or digital audio input signals. Digital audio input signals are supplied
through the serial audio input port as outlined in “Serial Audio Interfaces” on page 62. Analog audio input
signals are supplied through the internal ADC as outlined in “Analog Inputs” on page 61. The input source
is selected by the ADC/SP pin as shown in Table 14 below and can be changed at any time without caus-
ing any audible pops or clicks.
ADC/SP
Low
High
Selected Input Source
Digital Audio Inputs (Serial Port)
Analog Audio Inputs (ADC)
Table 14. Input Source Selection
In hardware mode, the serial audio input port supports both I²S and left-justified formats. The serial audio
interface format is selected by the I2S/LJ pin as shown in Table 15 below.
I2S/LJ
Low
High
Selected Serial Audio Interface Format
Left-Justified
I²S
Table 15. Serial Audio Interface Format Selection
6.2.4
PWM Channel Delay
In hardware mode, the CS4525 offsets the PWM switching edges between channels as a method of man-
aging switching noise and reducing radiated emissions.
The OUT3/OUT4 signal pair is delayed from the OUT1/OUT2 signal pair by 4 SYS_CLK cycles as shown
in Figure 23 below. The absolute delay time is calculated by multiplying the period SYS_CLK by 4.
OUT1
OUT2
OUT3
4 x TSYS_CLK
OUT4
Figure 23. Hardware Mode PWM Output Delay
DS726PP3
55
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