CS43L22 查看數據表（PDF） - Cirrus Logic

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CS43L22

Low Power, Stereo DAC w/Headphone & Speaker Amps

Cirrus Logic 

Confidential Draft

3/4/10

CS43L22

4.5 PWM Outputs

Note: The PWM speaker amplifiers should not be used in the 384x MCLK modes (18.4320 and

16.9344 MHz).

SPKAMUTE

SPKBMUTE

MUTE50/50

SPKMONO

SPKSWAP

SPKB=A

SPKAVOL[7:0]

SPKBVOL[7:0]

+0dB/-102dB

0.5dB steps

BATTCMP

VPREF[3:0]

VPLVL[7:0]

Battery

Compensation

from DSP

Engine

VOL

PWM

Modulator

Gate

Drive

PDN_SPKA[1:0]

PDN_SPKB[1:0]

SPKASHRT

SPKBSHRT

Figure 10. PWM Output Stage

Short

Circuit

Referenced Control Register Location

PWM Control

SPKxMUTE ......................... “Speaker Mute” on page 45

MUTE50/50 ......................... “Speaker Mute 50/50 Control” on page 46

SPKMONO .......................... “Speaker MONO Control” on page 46

SPKxVOL[7:0] ..................... “Speaker Volume Control” on page 52

SPKSWAP........................... “Speaker Channel Swap” on page 45

SPKB=A .............................. “Speaker Volume Setting B=A” on page 45

BATTCMP ........................... “Battery Compensation” on page 56

VPREF[3:0] ......................... “VP Reference” on page 57

VPLVL[7:0] .......................... “VP Voltage Level (Read Only)” on page 57

PDN_SPKx[1:0]................... “Speaker Power Control” on page 38

SPKxSHRT.......................... “Speaker Current Load Status (Read Only)” on page 57

+

-

A

+

-

B

Speaker

Outputs

26

DS792F2

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