CS4392(2002) 查看數據表（PDF） - Cirrus Logic

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CS4392
(Rev.:2002)

24-Bit, 192 kHz Stereo DAC with Volume Control

Cirrus Logic 

CS4392

4.0.2b I2C Read

To read from the device, follow the procedure below while adhering to the control port

Switching Specifications.

1) Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits

must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must

be 1. The eighth bit of the address byte is the R/W bit.

2) After transmitting an acknowledge (ACK), the device will then transmit the contents of

the register pointed to by the MAP. The MAP register will contain the address of the last

register written to the MAP, or the default address (see section 4.1) if an I2C read is the first

operation performed on the device.

3) Once the device has transmitted the contents of the register pointed to by the MAP, issue

an ACK.

4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive

registers. Continue providing a clock and issue an ACK after each byte until all the desired

registers are read, then initiate a STOP condition to the bus.

5) If the INCR bit is set to 0 and further I2C reads from other registers are desired, it is nec-

essary to initiate a STOP condition and follow the procedure detailed from steps 1 and 2

from the I2C Write instructions followed by step 1 of the I2C Read section. If no further

reads from other registers are desired, initiate a STOP condition to the bus.

N ote 1

SDA

001000

ADDR

AD0

R/W ACK

DATA

1 -8

ACK

DATA

1-8

ACK

SCL

S tart

Stop

Note: If operation is a w rite, this byte contains the Memory Address Pointer, MA P.

Figure 8. Control Port Timing, I2C Mode

DS459PP2

15

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