CS4391A 查看數據表（PDF） - Cirrus Logic

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CS4391A

24-Bit, 192 kHz Stereo DAC with Volume Control

Cirrus Logic 

CS4391A

4.5.5 Freeze (Bit 2)

Function:

This function allows modifications to the registers without the changes being taking effect until Freeze

is disabled. To make multiple changes in the Control port registers take effect simultaneously, set the

Freeze Bit, make all register changes, then Disable the Freeze bit.

4.5.6 Master Clock Divide (Bit 1)

Function:

This function allows the user to select an internal divide by 2 of the Master Clock. This selection is

required to access the higher Master Clock rates as shown in Table 9.

DS600PP3

21

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