CS4362-BQ 查看數據表（PDF） - Cirrus Logic
零件编号
产品描述 (功能)
生产厂家
CS4362-BQ Datasheet PDF : 40 Pages
| |||
CS4362
3.2.2 SERIAL AUDIO DATA CLOCK SOURCE (SDINXCLK)
Default = 0
0 - SDINx clocked by SCLK1 and LRCK1
1 - SDINx clocked by SCLK2 and LRCK2
Function:
The SDINxCLK bit specifies which SCLK/LRCK input pair is used to clock in the data on the given
SDINx line. For more details see “Clock Source Selection” on page 28.
3.3 Mode Control 3 (address 03h)
7
SZC1
1
6
SZC0
0
5
SNGLVOL
0
4
RMP_UP
0
3
Reserved
0
2
AMUTE
1
1
MUTEC1
0
0
MUTEC0
0
3.3.1 SOFT RAMP AND ZERO CROSS CONTROL (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel.
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock
periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes
or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel.
17
Share Link: 