CS4272-DZZ 查看數據表（PDF） - Cirrus Logic

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CS4272-DZZ

24-Bit, 192 kHz Stereo Audio CODEC

Cirrus Logic 

CS4272

SWITCHING CHARACTERISTICS - SPI CONTROL PORT

(Inputs: logic 0 = AGND, logic 1 = VL)

Parameter

SPI Mode

CCLK Clock Frequency.

RST Rising Edge to CS Falling.

CCLK Edge to CS Falling.

CS High Time Between Transmissions.

CS Falling to CCLK Edge.

CCLK Low Time.

CCLK High Time.

CDIN to CCLK Rising Setup Time.

CCLK Rising to DATA Hold Time.

Rise Time of CCLK and CDIN.

Fall Time of CCLK and CDIN.

Symbol

Min

fsclk

-

tsrs

500

(Note 24)

tspi

500

tcsh

1.0

tcss

20

tscl

82

tsch

82

tdsu

40

(Note 25)

tdh

15

(Note 26)

tr2

-

(Note 26)

tf2

-

Max

6

-

-

-

-

-

-

-

-

100

100

Unit

MHz

ns

ns

µs

ns

ns

ns

ns

ns

ns

ns

Notes: 24. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

25. Data must be held for sufficient time to bridge the transition time of CCLK.

26. For FSCK < 1 MHz

RST

t srs

CS

t spi t css

t scl t sch

t csh

CCLK

t r2

t f2

CDIN

t dsu t dh

Figure 7. SPI Control Port Timing

22

DS593F1

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