CS4270-DZZ 查看數據表（PDF） - Cirrus Logic
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CS4270-DZZ Datasheet PDF : 49 Pages
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CS4270
8.4.2 ADC HPF Freeze B (Bit 6)
Function:
When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC
offset value will be frozen and continuously subtracted from the conversion result. Section 5.2.7 “High-
Pass Filter and DC Offset Calibration” on page 26.
8.4.3 Digital Loopback (Bit 5)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to
Section 5.2.5 “Internal Digital Loopback” on page 26.
8.4.4 DAC Digital Interface Format (Bits 4:3)
Function:
The DAC Digital Interface Format and the options are detailed in Table 10 and Figures 9 through 11.
DAC_DIF1
0
0
1
1
DAC_DIF0
0
1
1
0
Description
Left-Justified, up to 24-bit data (default)
I²S, up to 24-bit data
Right-Justified, 16-bit Data
Right-Justified, 24-bit Data
Table 10. DAC Digital Interface Formats
Format
0
1
2
3
Figure
9
10
11
11
8.4.5 ADC Digital Interface Format (Bit 0)
Function:
The required relationship between LRCK, SCLK and SDOUT for the ADC is defined by the ADC Digital
Interface Format. The options are detailed in Table 11 and may be seen in Figures 9 and 10.
ADC_DIF
0
1
Description
Left-Justified, up to 24-bit data (default)
I²S, up to 24-bit data
Format
0
1
Table 11. ADC Digital Interface Formats
Figure
9
10
DS686PP1
37
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