CS4270 查看數據表（PDF） - Cirrus Logic
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CS4270 Datasheet PDF : 49 Pages
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CS4270
5.2.3 System Clocking
The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three
speed modes as shown in Table 4.
Mode
Sampling Frequency
Single-Speed
4-54 kHz
Double-Speed
50-108 kHz
Quad-Speed
100-216 kHz
Table 4. Speed Modes
5.2.4 Clock Ratio Selection
In Control Port Master Mode, the user must configure the mode bits (MCLK Freq<2:0>) to set the speed
mode and select the appropriate clock ratios. Depending on whether the CS4270 is in Master or Slave
Mode, different MCLK/LRCK and SCLK/LRCK ratios may be used. These ratios as well as the Control
Port Register Bits are shown in Table 5, Table 9 and Section 8.3 on page 36.
Single-Speed
Double-Speed
Quad-Speed
Single-Speed
MCLK/LRCK
256
384
512
768
1024
128
192
256
384
512
64
96
128
192
256
MCLK/LRCK
256
384
512
768
1024
Master Mode
SCLK/LRCK
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
Slave Mode
SCLK/LRCK
32, 64, 128
32, 48, 64, 96, 128
32, 64, 128
32, 48, 64, 96, 128
32, 64, 128
LRCK
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
LRCK
Fs
Fs
Fs
Fs
Fs
MCLK
Freq<2>
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
MCLK
Freq<2>
0
0
0
0
1
MCLK
Freq<1>
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
MCLK
Freq<1>
0
0
1
1
0
MCLK
Freq<0>
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
MCLK
Freq<0>
0
1
0
1
0
Table 5. Clock Ratios - Control Port Mode
DS686PP1
25
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