CS4220 查看數據表（PDF） - Cirrus Logic

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CS4220

24-Bit Stereo Audio Codec with 3V Interface

Cirrus Logic 

CS4220 CS4221

5. REGISTER DESCRIPTIONS - CS4221

Note: All registers are read/write in I2C mode and write-only in SPI mode, unless otherwise noted.

5.1 ADC Control (address 01h)

7

PDN

0

6

HPDR

0

5

HPDL

0

4

ADMR

0

3

ADML

0

2

CAL

0

1

CALP

0

0

CLKE

0

5.1.1 POWER DOWN ADC (PDN)

Default = 0

0 - Disabled

1 - Enabled

Function:

The ADC will enter a low-power state when this function is enabled.

5.1.2 LEFT AND RIGHT CHANNEL HIGH PASS FILTER DEFEAT (HPDR-HPDL)

Default = 0

0 - Disabled

1 - Enabled

Function:

The internal high-pass filter is defeated when this function is enabled. Control of the internal high-

pass filter is independent for the left and right channel.

5.1.3 LEFT AND RIGHT CHANNEL ADC MUTING (ADMR-ADML)

Default = 0

0 - Disabled

1 - Enabled

Function:

The output for the selected ADC channel will be muted when this function is enabled.

5.1.4 CALIBRATION CONTROL (CAL)

Default = 0

0 - Disabled

1 - Enabled

Function:

The device will automatically perform an offset calibration when brought out of reset, which last ap-

proximately 50 ms. When this function is enabled, a rising edge on the reset line will initiate an offset

calibration.

5.1.5 CALIBRATION STATUS (CALP) (READ ONLY)

Default = 0

0 - Calibration done

1 - Calibration in progress

DS284PP3

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