CMX838 查看數據表（PDF） - CML Microsystems Plc

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CMX838

FRS/PMR446/GMRS Family Radio Processor

CML Microsystems Plc 

FRS/PMR446/GMRS Family Radio Processor

CMX838

5.1.2.19 SUBAUDIO ANALOG CONTROL Register ($97)

Bit(s)

SUBAUDIO

FILTER INPUT

SELECT

Bit 15

Description

Bit 15 in conjunction with TX/RX bit (bit 7) of the SETUP Register ($80) controls the

input signal source of the subaudio filter according to the following table:

Bit 15

0

0

1

1

TX/ RX

0

1

0

1

RXIN pin

Encoder D/A

Encoder D/A

RXIN pin

Input Source

SUBAUDIO

LOW PASS

FILTER 1 GAIN

Bit 14

SUBAUDIO

HIGH PASS

FILTER/ LOW

PASS FILTER

SELECT

Bit 13

Bit 15 in conjunction with TX/RX form the DECODE control signal of the subaudio

analog block according to the above table. In normal operation, this bit should be a

logic ‘0’.

Bit 14 in conjunction with TX/RX bit (bit 7) of the SETUP Register ($80) controls the

gain of the subaudio low pass filter, which is the second subaudio filter stage. The low

pass filter gain is set according to the following table:

Bit 14

0

0

1

1

TX/ RX

0

+20

1

0

0

0

1

+20

Gain (dB)

The default gain setting is 0dB for TX mode and +20dB for RX mode. Setting gain to

+20dB in TX mode will overdrive the low pass filter resulting in distorted signals. This

bit should be a logic ‘0’ for normal operation.

Bit 13 in conjunction with TX/RX bit (bit 7) of the SETUP Register ($80) controls the

subaudio filter characteristic of the 2nd filter stage according to the following table:

Bit 13

0

0

1

1

TX/ RX

0

1

0

1

Characteristic

65Hz High Pass DC Blocking Filter

2kHz Low Pass Smoothing Filter

2kHz Low Pass Smoothing Filter

65Hz High Pass DC Blocking Filter

The nominal gain of this 2nd subaudio filter stage is 0dB for HPF mode and –18dB for

LPF mode. See Bit 7 description for setting Low Pass Filter 2 gain to 0dB. This bit

should be a logic ‘0’ for normal operation.

 2003 CML Microsystems Plc

43

D/838/8

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