CL-PS7111-VC-A 查看數據表（PDF） - Cirrus Logic

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CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

5.22 UART Bit Rate and Line Control Registers — UBRLCR1–2

31:19

Reserved

18:17

WRDLEN

16

FIFOEN

15

XSTOP

14

EVENPRT

13

PRTEN

12

BREAK

11:0

Bit rate divisor

The UART Bit Rate and Line Control registers are 19-bit read/write registers. A write to these registers

sets the bit rate and mode of operation for the internal UARTs.

Bit Description

31:19 Reserved

18:17 WRDLEN: This 2-bit field selects the word length as shown in the following table.

Bit

18

17

0

0

0

1

1

0

1

1

Word Length

5 bits

6 bits

7 bits

8 bits

16 FIFOEN: Set to enable FIFO buffering of Rx and Tx data. Clear to disable the FIFO, that is, set its depth to one byte.

15 XSTOP: Extra stop bit. Setting this bit causes the UART to transmit two stop bits after each data byte, clearing it trans-

mits one stop bit after each data byte.

14 EVENPRT: Even parity bit. Setting this bit sets parity generation and checking to even parity, clearing it sets odd parity.

This bit has no effect if the PRTEN bit is clear.

13 PRTEN: Parity enable bit. Setting this bit enables parity detection and generation.

12 BREAK: Setting this bit drives the Tx output active (high) to generate a break.

September 1997

PRELIMINARY DATA BOOK v2.0

65

REGISTER DESCRIPTIONS

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