CS5364-DQZR(2007) 查看數據表（PDF） - Cirrus Logic
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CS5364-DQZR Datasheet PDF : 41 Pages
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CS5364
4.6.3 Master Mode Clock Dividers
Figure 13 shows the configuration of the MCLK dividers and the sample rate dividers for Master Mode, in-
cluding the significance of each MCLK divider pin (in Stand-Alone Mode) or bit (in Control Port Mode).
SAMPLE RATE DIVIDERS
MCLK DIVIDERS
MCLK
0/1
0/1
0/1
÷1
÷1
÷1
÷ 1.5
÷2
÷2
÷ 256
Single
Speed
00
÷ 128
Double
Speed
01
÷ 64
Quad
10
Speed
M1 M0
LRCK/ FS
pin CLKMODE MDIV
bit CLKMODE MDIV1
n/a
MDIV0
÷4
Single
Speed
00
÷2
Double
Speed
01
÷1
Quad
Speed
10
SCLK
Figure 13. Master Mode Clock Dividers
4.6.4 Slave Mode Audio Clocking With Auto-Detect
In Slave Mode, CS5364 auto-detects speed mode, which eliminates the need to configure M1 and M0 when
changing among speed modes. The external MCLK is subject to clock dividers as set by the clock divider
pins in Stand-Alone Mode or the clock divider bits in Control Port Mode. The CS5364 compares the divided-
down, internal MCLK to the incoming LRCK/FS and sets the speed mode based on the MCLK/LRCK ratio
as shown in Figure 14.
External
MCLK
MCLK DIVIDERS
0/1
0/1
0/1
÷1
÷1
÷1
÷ 1.5
÷2
÷2
Internal
MCLK
÷LRCK
pin CLKMODE MDIV
n/a
LRCK
bit CLKMODE MDIV1 MDIV0
Figure 14. Slave Mode Auto-Detect Speed
SPEED MODE
256
128
64
Single-Speed
Double-Speed
Quad-Speed
24
DS625F2
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