CS5345 查看數據表（PDF） - Cirrus Logic

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CS5345

104 dB, 24-Bit, 192 kHz Stereo Audio ADC

Cirrus Logic 

CS5345

6.3 ADC Control - Address 04h

7

FM1

6

5

4

FM0

Reserved

DIF

6.3.1 Functional Mode (Bits 7:6)

3

Reserved

2

1

0

Mute

HPFFreeze

M/S

Function:

6.3.2

Selects the required range of sample rates.

FM1

0

0

1

1

FM0

0

1

0

1

Mode

Single-Speed Mode: 4 to 50 kHz sample rates

Double-Speed Mode: 50 to 100 kHz sample rates

Quad-Speed Mode: 100 to 200 kHz sample rates

Reserved

Table 6. Functional Mode Selection

Digital Interface Format (Bit 4)

Function:

The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface Format

bit. The options are detailed in Table 7 and may be seen in Figure 3 and Figure 4.

6.3.3

DIF

Description

Format

0

Left-Justified, up to 24-bit data (default)

0

1

I²S, up to 24-bit data

1

Mute (Bit 2)

Table 7. Digital Interface Formats

Figure

3

4

Function:

6.3.4

When this bit is set, the serial audio output of the both channels is muted.

High-Pass Filter Freeze (Bit 1)

Function:

6.3.5

When this bit is set, the internal high-pass filter is disabled.The current DC offset value will be frozen and

continue to be subtracted from the conversion result. See “High-Pass Filter and DC Offset Calibration” on

page 24.

Master / Slave Mode (Bit 0)

Function:

This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master

Mode, while clearing this bit selects Slave Mode.

32

DS658F2

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