CS5345(2004) 查看數據表（PDF） - Cirrus Logic

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CS5345
(Rev.:2004)

105 dB, 24-Bit, 192 kHz Stereo Audio ADC

Cirrus Logic 

CS5345

Table 10. PGA Soft Cross or Zero Cross Mode Selection

6.8.2

PGASoft

PGAZeroCross

Mode

0

0

Changes to affect immediately

0

1

Zero Cross enabled

1

0

Soft Ramp enabled

1

1

Soft Ramp and Zero Cross enabled (default)

Analog Input Selection (Bits 2:0)

Function:

These bits are used to select the input source for the PGA and ADC. Please see Table 11 below.

Sel2

0

0

0

0

1

1

1

1

Table 11. Analog Input Multiplexer Selection

Sel1

0

0

1

1

0

0

1

1

Sel0

0

1

0

1

0

1

0

1

PGA/ADC Input

Microphone Level Inputs (+32 dB Gain Enabled)

Line Level Input Pair 1

Line Level Input Pair 2

Line Level Input Pair 3

Line Level Input Pair 4

Line Level Input Pair 5

Line Level Input Pair 6

Reserved

6.9 Active Level Control - Address 0Ch

7

Reserved

6

Reserved

5

Reserved

4

Reserved

3

Reserved

2

Reserved

1

Reserved

0

Active_H/L

6.9.1 Active High/Low (Bit 0)

Function:

When this bit is set, the INT pin will function as an active high CMOS driver.

When this bit is cleared, the INT pin will function as an active low open drain driver and will require an

external pull-up resistor for proper operation.

6.10 Interrupt Status - Address 0Dh

7

Reserved

6

5

4

3

2

1

Reserved

Reserved

Reserved

ClkErr

Reserved

Ovfl

0

Undrfl

For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once

since the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred

since the last reading of the register. Status bits that are masked off in the associated mask register

will always be ‘0’ in this register. This register defaults to 00h.

6.10.1 Clock Error (Bit 3)

Function:

Indicates the occurrence of a clock error condition.

33

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