CS5345(2004) 查看數據表（PDF） - Cirrus Logic

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CS5345
(Rev.:2004)

105 dB, 24-Bit, 192 kHz Stereo Audio ADC

Cirrus Logic 

CS5345

6. REGISTER DESCRIPTION

6.1 Chip ID - Register 01h

B7

PART3

B6

PART2

B5

PART1

B4

PART0

B3

REV3

B2

REV2

B1

REV1

B0

REV0

Function:

This register is Read-Only. Bits 7 through 4 are the part number ID which is 1110b (0Eh) and the re-

maining bits (3 through 0) are for the chip revision.

6.2 Power Control - Address 02h

7

Freeze

6

Reserved

5

Reserved

4

Reserved

3

PDN_MIC

2

PDN_ADC

1

Reserved

0

PDN

6.2.1 Freeze (Bit 7)

Function:

This function allows modifications to be made to certain control port bits without the changes taking

effect until the Freeze bit is disabled. To make multiple changes to these bits take effect simulta-

neously, set the Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the

Freeze function are listed in Table 4 below.

Table 4. Freeze-able Bits

Name

Mute

Gain[5:0]

Gain[5:0]

Register

04h

07h

08h

Bit(s)

2

5:0

5:0

6.2.2 Power Down MIC (Bit 3)

Function:

The microphone preamplifier block will enter a low-power state whenever this bit is set.

6.2.3 Power Down ADC (Bit 2)

Function:

The ADC pair will remain in a reset state whenever this bit is set.

6.2.4 Power Down Device (Bit 0)

Function:

The device will enter a low-power state whenever this bit is set. The power-down bit is set by default

and must be cleared before normal operation can occur. The contents of the control registers are re-

tained when the device is in power-down.

6.3 ADC Control - Address 04h

7

FM1

6

5

4

3

2

1

0

FM0

Reserved

DIF

Reserved

Mute

HPFFreeze

M/S

29

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