CS4361(2005) 查看數據表（PDF） - Cirrus Logic

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CS4361
(Rev.:2005)

20-pin, 24-bit, 192 kHz, 6-channel D/A Converter

Cirrus Logic 

CS4361

LRCK

SCLK

Left Channel

Right Channel

SDATA 0

23 22 21 20 19 18

76543210

23 22 21 20 19 18

76543210

Interna3l2ScloCcksLK Mode

External SCLK Mode

Right Justified, 24-Bit Data

INT SCLK = 64 Fs if

MCLK/LRCK = 1024, 512, 256, 128, or 64

INT SCLK = 48 Fs if

MCLK/LRCK = 768, 384, 192, or 96

INT SCLK = 72 Fs if

MCLK/LRCK = 1152

Right Justified, 24-Bit Data

Data Valid on Rising Edge of SCLK

SCLK Must Have at Least 48 Cycles per LRCK Period

Figure 9. CS4361 Data Format (Right Justified 24)

LRCK

SCLK

Left Channel

Right Channel

SDATA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Internal32SclCockLs K Mode

Right Justified, 16-Bit Data

INT SCLK = 32 Fs if

MCLK/LRCK = 1024, 512, 256, 128, or 64

INT SCLK = 48 Fs if

MCLK/LRCK = 768, 384, 192, or 96

INT SCLK = 72 Fs if

MCLK/LRCK = 1152

External SCLK Mode

Right Justified, 16-Bit Data

Data Valid on Rising Edge of SCLK

SCLK Must Have at Least 32 Cycles per LRCK Period

Figure 10. CS4361 Data Format (Right Justified 16)

14

DS672A2

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