CS42L51 查看數據表（PDF） - Cirrus Logic

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CS42L51

Low Power, Stereo CODEC with Headphone Amp

Cirrus Logic 

CS42L51

6.21 Limiter Release Rate Register (Address 1Ah)

7

LIMIT_EN

6

LIMIT_ALL

5

RRATE5

4

RRATE4

3

RRATE3

2

RRATE2

1

RRATE1

0

RRATE0

Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.

Peak Detect and Limiter Enable (LIMIT_EN)

Default: 0

0 - Disabled

1 - Enabled

Function:

Limits the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting

is performed by digital attenuation. Note: When the limiter is enabled, the AOUT Volume is automatically

controlled and should not be adjusted manually. Alternative volume control may be realized using the

PCMMIXx_VOL[6:0] bits.

Peak Signal Limit All Channels (LIMIT_ALL)

Default: 1

0 - Individual Channel

1 - Both channel A & B

Function:

When set to 0, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the spe-

cific channel indicating clipping. The other channels will not be affected.

When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on both

channels in response to any single channel indicating clipping.

Limiter RELEASE Rate (RRATE[5:0])

Default: 111111

Binary Code

000000

···

111111

Release Time

Fastest Release

···

Slowest Release

Function:

Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in

the limiter threshold register, and returns the analog output level to the AOUTx_VOL[7:0] setting.

The limiter release rate is user selectable but is also a function of the sampling frequency, Fs, and the

DAC_SZC setting unless the disable bit is enabled.

DS679F1

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