CS4228 查看數據表（PDF） - Cirrus Logic
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CS4228 Datasheet PDF : 30 Pages
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CS4228
Serial Port Mode
Address 0x0D
7
DCK1
1
DCK1:0
6
DCK0
0
5
DMS1
0
4
DMS0
0
3
RESERVED
0
2
DDF2
1
Sets the number of Serial Clocks (SCLK) per Fs period (LRCLK)
DCK1:0
0
1
2
3
BRM (Fs)
32 (1)
48 (2)
*64
128
HRM (Fs)
16 (3)
24 (4)
32 (1)
64
1
DDF1
0
DMS1:0
DDF2:0
Notes: 1. All formats will default to 16 bits
2. External Slave mode only
3. Only valid for left justified and I2S modes
4. Only valid for left justified and I2S, External Slave mode only
Sets the master/slave mode of the serial audio port
*0 - Slave (External LRCLK, SCLK)
1 - Reserved
2 - Reserved
3 - Master (No 48 Fs SCLK in BRM, no 24 Fs SCLK in HRM)
Serial Port Data Format
0 - Right Justified, 24-bit
1 - Right Justified, 20-bit
2 - Right Justified, 16-bit
3 - Left Justified, maximum 24-bit
*4 - I2S compatible, maximum 24-bit
5 - One-line Data Mode, available in BRM only
6 - Reserved
7 - Reserved
Chip Status
Address 0x0E
7
CLKERR
X
CLKERR
ADCOVL
6
5
4
3
2
1
ADCOVL
RESERVED
X
0
0
0
0
0
Clocking system status, read only
0 - No Error
1 - No MCLK is present, or a request for clock change is in progress
ADC overflow bit, read only
0 - No overflow
1 - ADC overflow has occurred
0
DFF0
0
0
0
DS307PP1
23
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