C8051F93X-C8051F92X 查看數據表（PDF） - Silicon Laboratories

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C8051F93X-C8051F92X

Single/Dual Battery, 0.9–3.6 V, 64/32 kB, SmaRTClock, 10-Bit ADC MCU

Silicon Laboratories 

C8051F93x-C8051F92x

Table 24.1. SPI Slave Timing Parameters

Parameter

Description

Min

Max

Units

Master Mode Timing* (See Figure 24.8 and Figure 24.9)

TMCKH

SCK High Time

1 x TSYSCLK

—

ns

TMCKL

SCK Low Time

1 x TSYSCLK

—

ns

TMIS

MISO Valid to SCK Shift Edge

1 x TSYSCLK + 20

—

ns

TMIH

SCK Shift Edge to MISO Change

0

Slave Mode Timing* (See Figure 24.10 and Figure 24.11)

—

ns

TSE

NSS Falling to First SCK Edge

2 x TSYSCLK

—

ns

TSD

Last SCK Edge to NSS Rising

2 x TSYSCLK

—

ns

TSEZ

NSS Falling to MISO Valid

—

4 x TSYSCLK ns

TSDZ

NSS Rising to MISO High-Z

—

4 x TSYSCLK ns

TCKH

SCK High Time

5 x TSYSCLK

—

ns

TCKL

SCK Low Time

5 x TSYSCLK

—

ns

TSIS

MOSI Valid to SCK Sample Edge

2 x TSYSCLK

—

ns

TSIH

SCK Sample Edge to MOSI Change

2 x TSYSCLK

—

ns

TSOH

TSLH

SCK Shift Edge to MISO Change

Last SCK Edge to MISO Change 

(CKPHA = 1 ONLY)

—

6 x TSYSCLK

4 x TSYSCLK ns

8 x TSYSCLK ns

*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).

282

Rev. 1.3

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