C8051F93X-C8051F92X 查看數據表（PDF） - Silicon Laboratories
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C8051F93X-C8051F92X
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C8051F93X-C8051F92X Datasheet PDF : 330 Pages
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C8051F93x-C8051F92x
19.4. Special Function Registers for Selecting and Configuring the System Clock
The clocking sources on C8051F93x-C8051F92x devices are enabled and configured using the OSCICN,
OSCICL, OSCXCN and the SmaRTClock internal registers. See Section “20. SmaRTClock (Real Time
Clock)” on page 200 for SmaRTClock register descriptions. The system clock source for the MCU can be
selected using the CLKSEL register. To minimize active mode current, the oneshot timer which sets Flash
read time should by bypassed when the system clock is greater than 10 MHz. See the FLSCL register
description for details.
The clock selected as the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. When switching
between two clock divide values, the transition may take up to 128 cycles of the undivided clock source.
The CLKRDY flag can be polled to determine when the new clock divide value has been applied. The clock
divider must be set to "divide by 1" when entering suspend or sleep mode.
The system clock source may also be switched on-the-fly. The switchover takes effect after one clock
period of the slower oscillator.
SFR Definition 19.1. CLKSEL: Clock Select
Bit
7
6
5
4
3
2
1
0
Name CLKRDY
CLKDIV[2:0]
CLKSEL[2:0]
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
1
1
0
1
0
0
SFR Page = All Pages; SFR Address = 0xA9
Bit
Name
Function
7
CLKRDY System Clock Divider Clock Ready Flag.
0: The selected clock divide setting has not been applied to the system clock.
1: The selected clock divide setting has been applied to the system clock.
6:4 CLKDIV[2:0] System Clock Divider Bits.
Selects the clock division to be applied to the undivided system clock source.
000: System clock is divided by 1.
001: System clock is divided by 2.
010: System clock is divided by 4.
011: System clock is divided by 8.
100: System clock is divided by 16.
101: System clock is divided by 32.
110: System clock is divided by 64.
111: System clock is divided by 128.
3
Unused. Read = 0b. Must Write 0b.
2:0 CLKSEL[2:0] System Clock Select.
Selects the oscillator to be used as the undivided system clock source.
000: Precision Internal Oscillator.
001: External Oscillator.
011: SmaRTClock Oscillator.
100: Low Power Oscillator.
All other values reserved.
Rev. 1.3
197
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