C8051F93X-C8051F92X 查看數據表（PDF） - Silicon Laboratories

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C8051F93X-C8051F92X

Single/Dual Battery, 0.9–3.6 V, 64/32 kB, SmaRTClock, 10-Bit ADC MCU

Silicon Laboratories 

C8051F93x-C8051F92x

15. Cyclic Redundancy Check Unit (CRC0)

C8051F93x-C8051F92x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC

using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register.

CRC0 posts the 16-bit or 32-bit result to an internal register. The internal result register may be accessed

indirectly using the CRC0PNT bits and CRC0DAT register, as shown in Figure 15.1. CRC0 also has a bit

reverse register for quick data manipulation.

CRC0IN

8

8

Automatic CRC

Controller

Flash

Memory

CRC0SEL

CRC0INIT

CRC0VAL

CRC0PNT1

CRC0PNT0

CRC0FLIP

Write

CRC Engine

32

RESULT

8

88

8

CRC0AUTO

CRC0CNT

4 to 1 MUX

CRC0FLIP

Read

8

CRC0DAT

Figure 15.1. CRC0 Block Diagram

15.1. 16-bit CRC Algorithm

The C8051F93x-C8051F92x CRC unit calculates the 16-bit CRC MSB-first, using a poly of 0x1021. The

following describes the 16-bit CRC algorithm performed by the hardware:

1. XOR the input with the most-significant bits of the current CRC result. If this is the first iteration

of the CRC unit, the current CRC result will be the set initial value 

(0x0000 or 0xFFFF).

2a. If the MSB of the CRC result is set, left-shift the CRC result and XOR the result with the

selected polynomial (0x1021).

2b. If the MSB of the CRC result is not set, left-shift the CRC result.

Repeat steps 2a/2b for the number of input bits (8). The algorithm is also described in the following

example.

Rev. 1.3

167

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