C8051F93X-C8051F92X 查看數據表（PDF） - Silicon Laboratories

零件编号

产品描述 (功能)

生产厂家

C8051F93X-C8051F92X

Single/Dual Battery, 0.9–3.6 V, 64/32 kB, SmaRTClock, 10-Bit ADC MCU

Silicon Laboratories 

C8051F93x-C8051F92x

SFR Definition 12.5. EIE2: Extended Interrupt Enable 2

Bit

7

6

5

4

3

2

1

0

Name

ESPI1 ERTC0F EMAT EWARN

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

SFR Page = All Pages;SFR Address = 0xE7

Bit Name

Function

7:4 Unused Unused.

Read = 0000b. Write = Don’t care.

3 ESPI1 Enable Serial Peripheral Interface (SPI1) Interrupt.

This bit sets the masking of the SPI1 interrupts.

0: Disable all SPI1 interrupts.

1: Enable interrupt requests generated by SPI1.

2 ERTC0F Enable SmaRTClock Oscillator Fail Interrupt.

This bit sets the masking of the SmaRTClock Alarm interrupt.

0: Disable SmaRTClock Alarm interrupts.

1: Enable interrupt requests generated by SmaRTClock Alarm.

1 EMAT Enable Port Match Interrupts.

This bit sets the masking of the Port Match Event interrupt.

0: Disable all Port Match interrupts.

1: Enable interrupt requests generated by a Port Match.

0 EWARN Enable VDD/DC+ Supply Monitor Early Warning Interrupt.

This bit sets the masking of the VDD/DC+ Supply Monitor Early Warning interrupt.

0: Disable the VDD/DC+ Supply Monitor Early Warning interrupt.

1: Enable interrupt requests generated by VDD/DC+ Supply Monitor.

144

Rev. 1.3

Share Link: