C8051F91X-C8051F90X 查看數據表（PDF） - Silicon Laboratories

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C8051F91X-C8051F90X

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

Table 24.1. SPI Slave Timing Parameters

Parameter

Description

Master Mode Timing* (See Figure 24.8 and Figure 24.9)

TMCKH

SCK High Time

TMCKL

SCK Low Time

TMIS

MISO Valid to SCK Shift Edge

TMIH

SCK Shift Edge to MISO Change

Slave Mode Timing* (See Figure 24.10 and Figure 24.11)

TSE

NSS Falling to First SCK Edge

TSD

Last SCK Edge to NSS Rising

TSEZ

NSS Falling to MISO Valid

TSDZ

NSS Rising to MISO High-Z

TCKH

SCK High Time

TCKL

SCK Low Time

TSIS

MOSI Valid to SCK Sample Edge

TSIH

SCK Sample Edge to MOSI Change

TSOH

SCK Shift Edge to MISO Change

TSLH

Last SCK Edge to MISO Change 

(CKPHA = 1 ONLY)

Min

Max

Units

1 x TSYSCLK

—

ns

1 x TSYSCLK

—

ns

1 x TSYSCLK + 20

—

ns

0

—

ns

2 x TSYSCLK

2 x TSYSCLK

—

—

5 x TSYSCLK

5 x TSYSCLK

2 x TSYSCLK

2 x TSYSCLK

—

6 x TSYSCLK

—

ns

—

ns

4 x TSYSCLK ns

4 x TSYSCLK ns

—

ns

—

ns

—

ns

—

ns

4 x TSYSCLK ns

8 x TSYSCLK ns

*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).

Rev. 1.0

269

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