C8051F91X-C8051F90X 查看數據表（PDF） - Silicon Laboratories

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C8051F91X-C8051F90X

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

24. Enhanced Serial Peripheral Interface (SPI0 and SPI1)

The enhanced serial peripheral interfaces (SPI0 and SPI1) provide access to two identical, flexible, full-

duplex synchronous serial busses. Both SPI0 and SPI1 will be referred to collectively as SPIn. SPIn can

operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and

slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPIn in

slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on

the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be config-

ured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose

port I/O pins can be used to select multiple slave devices in master mode.

SFR Bus

SPInCKR

SPInCFG

SPInCN

SYSCLK

Clock Divide

Logic

SPI CONTROL LOGIC

Data Path

Control

Pin Interface

Control

SPIn IRQ

Tx Data

MOSI

C

SPInDAT

SCK R

Transmit Data Buffer

O

Shift Register

76543210

Pin

S

Control

Logic

Rx Data

MISO

S

B

A

R

Receive Data Buffer

NSS

Write

SPI0DAT

Read

SPI0DAT

SFR Bus

Figure 24.1. SPI Block Diagram

Port I/O

Rev. 1.0

255

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