C8051F91X-C8051F90X 查看數據表（PDF） - Silicon Laboratories

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C8051F91X-C8051F90X

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

13.6. Minimizing Flash Read Current

The Flash memory in the C8051F91x-C8051F90x devices is responsible for a substantial portion of the

total digital supply current when the device is executing code. Below are suggestions to minimize Flash

read current.

1. Use idle, suspend, or sleep modes while waiting for an interrupt, rather than polling the inter-

rupt flag. Idle Mode is particularly well-suited for use in implementing short pauses, since the

wake-up time is no more than three system clock cycles. See the Power Management chapter

for details on the various low-power operating modes.

2. C8051F91x-C8051F90x devices have a one-shot timer that saves power when operating at

system clock frequencies of 14 MHz or less. The one-shot timer generates a minimum-dura-

tion enable signal for the Flash sense amps on each clock cycle in which the Flash memory is

accessed. This allows the Flash to remain in a low power state for the remainder of the long

clock cycle.

At clock frequencies above 14 MHz, the system clock cycle becomes short enough that the

one-shot timer no longer provides a power benefit. Disabling the one-shot timer at higher fre-

quencies reduces power consumption. The one-shot is enabled by default, and it can be dis-

abled (bypassed) by setting the BYPASS bit (FLSCL.6) to logic 1. To re-enable the one-shot,

clear the BYPASS bit to logic 0.

3. Flash read current depends on the number of address lines that toggle between sequential

Flash read operations. In most cases, the difference in power is relatively small (on the order

of 5%).

The Flash memory is organized in rows of 64 bytes. A substantial current increase can be

detected when the read address jumps from one row in the Flash memory to another. Con-

sider a 3-cycle loop (e.g., SJMP $, or while(1);) which straddles a Flash row boundary. The

Flash address jumps from one row to another on two of every three clock cycles. This can

result in a current increase of up 30% when compared to the same 3-cycle loop contained

entirely within a single row.

To minimize the power consumption of small loops, it is best to locate them within a single row,

if possible. To check if a loop is contained within a Flash row, divide the starting address of the

first instruction in the loop by 64. If the remainder (result of modulo operation) plus the length

of the loop is less than 63, then the loop fits inside a single Flash row. Otherwise, the loop will

be straddling two adjacent Flash rows. If a loop executes in 20 or more clock cycles, then the

transitions from one row to another will occur on relatively few clock cycles, and any resulting

increase in operating current will be negligible.

To write software that is compatible with all devices in the ‘F93x-’F92x and ‘F91x-’F90x

product families, the Flash row size should be considered 64 bytes.

Rev. 1.0

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