C8051F38C-GMR 查看數據表（PDF） - Silicon Laboratories

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C8051F38C-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

27.4. Watchdog Timer Mode

A programmable watchdog timer (WDT) function is available through the PCA Module 4. The WDT is used

to generate a reset if the time between writes to the WDT update register (PCA0CPH4) exceed a specified

limit. The WDT can be configured and enabled/disabled as needed by software.

With the WDTE bit set in the PCA0MD register, Module 4 operates as a watchdog timer (WDT). The Mod-

ule 4 high byte is compared to the PCA counter high byte; the Module 4 low byte holds the offset to be

used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some

PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset

shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and option-

ally re-configured and re-enabled if it is used in the system).

27.4.1. Watchdog Timer Operation

While the WDT is enabled:

 PCA counter is forced on.

 Writes to PCA0L and PCA0H are not allowed.

 PCA clock source bits (CPS2–CPS0) are frozen.

 PCA Idle control bit (CIDL) is frozen.

 Module 4 is forced into software timer mode.

 Writes to the Module 4 mode register (PCA0CPM4) are disabled.

While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run

until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but

user software has not enabled the PCA counter. If a match occurs between PCA0CPH4 and PCA0H while

the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a

write of any value to PCA0CPH4. Upon a PCA0CPH4 write, PCA0H plus the offset held in PCA0CPL4 is

loaded into PCA0CPH4 (See Figure 27.10).

PCA0MD

C WW

I DD

DT L

L EC

K

CCCE

PPPC

SSSF

210

PCA0CPH4

8-bit

Enable Comparator

Match

Reset

PCA0CPL4

8-bit Adder

PCA0H

PCA0L Overflow

Write to

PCA0CPH4

Adder

Enable

Figure 27.10. PCA Module 4 with Watchdog Timer Enabled

308

Rev. 1.4

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