
C8051F380/1/2/3/4/5/6/7/C
TMR3CN
TTTTTTTT
FFF 3 3R3 3
3 3 3CS3CX
HL LEP SC
E L SL
NI K
T
SYSCLK / 12
0
External Clock / 8
1
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
TMR3RLH Capture
0
1
SYSCLK
TR3
TCLK TMR3H
To ADC
TMR3RLL Capture
1
TCLK TMR3L
0
USB Start-of-Frame (SOF)
0
Low-Frequency Oscillator
Falling Edge
1
T3CSS
Figure 26.11. Timer 3 Capture Mode (T3SPLIT = 0)
Enable
Interrupt
284
Rev. 1.4