
C8051F380/1/2/3/4/5/6/7/C
TMR2CN
TTTTTTTT
FFF 2 2R2 2
2 2 2CS2CX
HL LEP SC
E L SL
NI
K
T
SYSCLK / 12
0
External Clock / 8
1
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
0
TR2
1
SYSCLK
TMR2RLH Capture
TCLK TMR2H
To SMBus
TMR2RLL Capture
1
TCLK TMR2L
To ADC,
SMBus
0
USB Start-of-Frame (SOF)
0
Low-Frequency Oscillator
Falling Edge
1
T2CSS
Figure 26.7. Timer 2 Capture Mode (T2SPLIT = 0)
Enable
Interrupt
Rev. 1.4
277