C8051F38C-GMR 查看數據表（PDF） - Silicon Laboratories
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C8051F38C-GMR Datasheet PDF : 321 Pages
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C8051F380/1/2/3/4/5/6/7/C
Table 25.1. SPI Slave Timing Parameters
Parameter Description
Min
Max
Units
Master Mode Timing (See Figure 25.8 and Figure 25.9)
TMCKH
SCK High Time
1 x TSYSCLK
—
ns
TMCKL
SCK Low Time
1 x TSYSCLK
—
ns
TMIS
MISO Valid to SCK Shift Edge
1 x TSYSCLK + 20
—
ns
TMIH
SCK Shift Edge to MISO Change
0
—
ns
Slave Mode Timing (See Figure 25.10 and Figure 25.11)
TSE
TSD
TSEZ
TSDZ
TCKH
TCKL
TSIS
TSIH
TSOH
TSLH
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
Last SCK Edge to MISO Change
(CKPHA = 1 ONLY)
2 x TSYSCLK
2 x TSYSCLK
—
—
5 x TSYSCLK
5 x TSYSCLK
2 x TSYSCLK
2 x TSYSCLK
—
6 x TSYSCLK
—
ns
—
ns
4 x TSYSCLK ns
4 x TSYSCLK ns
—
ns
—
ns
—
ns
—
ns
4 x TSYSCLK ns
8 x TSYSCLK ns
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
262
Rev. 1.4
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