C8051F362-GM2 查看數據表（PDF） - Silicon Laboratories

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C8051F362-GM2

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select

SFR Page: all pages

SFR Address: 0xBA

R

R

–

–

Bit7

Bit6

R

R/W

R/W

R/W

R/W

R/W

Reset Value

–

AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 00000000

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bits 7–5: UNUSED. Read = 000b; Write = don’t care.

Bits 4–0: AMX0N4–0: AMUX0 Negative Input Selection.

Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended

mode. For all other Negative Input selections, ADC0 operates in Differential mode.

AMX0N4-0

ADC0 Negative Input

00000(1)

00001(1)

P1.0(1)

P1.1(1)

00010(1)

P1.2(1)

00011(1)

00100

P1.3(1)

P1.4

00101

00110

P1.5

P1.6

00111

01000

P1.7

P2.0

01001

P2.1

01010

01011

P2.2

P2.3

01100

01101

P2.4

P2.5

01110

01111

P2.6

P2.7

10000

P3.0

10001(2)

P3.1(2)

10010(2)

10011(2)

P3.2(2)

P3.3(2)

10100(2)

P3.4(2)

10101–11101

11110

RESERVED

VREF

11111

GND

Notes:

1. Only applies to C8051F361/2/6/7/8/9 (32-pin and 28-pin); selection

RESERVED on C8051F360 (48-pin) device.

2. Only applies to C8051F360/1/6/8 (48-pin and 32-pin); selection RESERVED

on C8051F362/7/9 (28-pin) devices.

Rev. 1.0

55

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