C8051F362-GM2 查看數據表（PDF） - Silicon Laboratories
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C8051F362-GM2 Datasheet PDF : 288 Pages
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C8051F360/1/2/3/4/5/6/7/8/9
real-time clock functionality, where the PCA is clocked by an external source while the internal oscillator
drives the system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally,
Capture/Compare Module 5 offers watchdog timer (WDT) capabilities. Following a system reset, Module 5
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
PCA
CLOCK
MUX
16-Bit Counter/Timer
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4
Capture/Compare
Module 5
Crossbar
Port I/O
Figure 1.10. PCA Block Diagram
1.7. 10-Bit Analog to Digital Converter
The C8051F360/1/2/6/7/8/9 devices include an on-chip 10-bit SAR ADC with up to 21 channels for the dif-
ferential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with
an INL and DNL of ±1 LSB. The ADC system includes a configurable analog multiplexer that selects both
positive and negative ADC inputs. Ports1-3 are available as an ADC inputs; additionally, the on-chip Tem-
perature Sensor output and the power supply voltage (VDD) are available as ADC inputs. User firmware
may shut down the ADC to save power.
Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an
external convert start signal (CNVSTR). This flexibility allows the start of conversion to be triggered by soft-
ware events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indi-
Rev. 1.0
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