AT45DB321C-CU(2006) 查看數據表（PDF） - Atmel Corporation

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AT45DB321C-CU
(Rev.:2006)

32-megabit 2.7 volt DataFlash®

Atmel Corporation 

13.5 Reset Timing

CS

SCK

RESET

SO

HIGH IMPEDANCE

AT45DB321C

tREC

tRST

tCSS

HIGH IMPEDANCE

SI

Note: The CS signal should be in the high state before the RESET signal is deasserted.

13.6 Command Sequence for Read/Write Operations (except Status Register Read)

SI

CMD 8 bits 8 bits 8 bits

MSB

r XXX XXXX XXXX XXXX XXXX XXXX

LSB

Reserved for Page Address

larger densities (PA12-PA0)

Byte/Buffer Address

(BA9-BA0/BFA9-BFA0)

Notes:

1. “r” designates bits reserved for larger densities.

2. It is recommended that “r” be a logical “0” for densities of 32M bits or smaller.

3. For densities larger than 32M bits, the “r” bit becomes the most significant Page Address bit for the appropriate density.

25

3387L–DFLASH–6/06

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