AM186ES-40VIW 查看數據表（PDF） - InnovASIC, Inc

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AM186ES-40VIW

8-Bit/16-Bit Microcontrollers

InnovASIC, Inc 

IA186ES/IA188ES

8-Bit/16-Bit Microcontrollers

Data Sheet

November 15, 2011

during both bus hold and reset. These outputs are asserted with the ad address bus over a

256 byte range each.

2.2.28 pcs2_n/cts1_n/enrx1_n/pio18—Peripheral Chip Select 2 (synchronous

output)/Clear-to-Send 1 (asynchronous input)/Enable-Receiver-Request 1

(asynchronous input)

The pcs2_n signal provides an indication that a memory access is under way for the third region

of the peripheral memory block (I/O or memory address space). The base address of the

peripheral memory block is programmable. The pcs2_n is held high during both bus hold and

reset. This output is asserted with the ad address bus over a 256-byte range.

The cts1_n is the Clear-to-Send signal for asynchronous serial port 1 when the ENRX1 bit

(Bit [6]) in the auxiliary control register (AUXCON) is 0 and hardware flow control is enabled

for this port (FC bit [Bit (9)] in the serial port 1 control register [SP1CT]). This signal controls

the transmission of data from the serial port transmit register 1. When this signal is asserted, the

transmitter begins sending out a frame of data if any is in the transmit register, whereas if the

signal is deasserted, the data will be held in the transmit register. The signal is checked at the

beginning of each frame of transmit data.

The enrx1_n is the Enable-Receiver-Request for asynchronous serial port 1 when the enrx1 bit

(Bit [6]) in the auxiliary control register (AUXCON) is 1 and hardware flow control is enabled

for this port (FC bit [Bit (9)] in the serial port 1 control register [SP1CT]). This signal enables

the receiver of asynchronous serial port 1.

2.2.29 pcs3_n/rts1_n/rtr1_n/pio18—Peripheral Chip Select 3 (synchronous

output)/Ready-to-Send 1 (asynchronous output)/Ready-to-Receive 1

(asynchronous input)

The pcs3_n signal provides an indication that a memory access is under way for the fourth region

of the peripheral memory block (I/O or memory address space). The base address of the

Peripheral memory block is programmable. The pcs3_n is held high during both bus hold and

reset. This output is asserted with the ad address bus over a 256-byte range.

The rts1-n is the Ready-to-Send signal for asynchronous serial port 1 when the RTS1 bit (Bit [5])

in the auxiliary control register (AUXCON) is 1 and hardware flow control is enabled for this

port (FC bit [Bit (9)] in the serial port 1 control register [SP1CT]). This signal is asserted when

the serial port transmit register contains untransmitted data.

The rtr1-n is the Ready-to-Receive signal for asynchronous serial port 1 when the rts1 bit

(Bit [5]) in the auxiliary control register (AUXCON) is 0 and hardware flow control is enabled

for this port (FC bit [Bit (9)] in the serial port 1 control register [SP1CT]). This signal is asserted

when the serial port receive register does not contain valid, unread data.

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