CS4341A-KSZ 查看數據表（PDF） - Cirrus Logic
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CS4341A-KSZ Datasheet PDF : 34 Pages
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CS4341A
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE
(Inputs: Logic 0 = AGND, Logic 1 = VA)
I2C Mode
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
RST Rising Edge to Start
tirs
500
Bus Free Time Between Transmissions
tbuf
4.7
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
Clock Low time
tlow
4.7
Clock High Time
thigh
4.0
Setup Time for Repeated Start Condition
tsust
4.7
SDA Hold Time from SCL Falling
(Note 7)
thdd
0
SDA Setup time to SCL Rising
tsud
250
Rise Time of SCL
(Note 8)
trc
-
Fall Time SCL
tfc
-
Rise Time of SDA
trd
-
Fall Time SDA
tfd
-
Setup Time for Stop Condition
tsusp
4.7
100
kHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
25
ns
25
ns
1
µs
300
ns
-
µs
Notes: 7. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
8. See “Rise Time for Control Port Clock” on page 11. for a recommended circuit to meet rise time
specification.
RST
t irs
Stop
S ta rt
R epeated
S ta rt
SDA
t buf
t hdst
t high
t hdst
tf
SCL
t low
t hdd
t sud
t sust
tr
Figure 19. Control Port Timing - I2C Mode
Stop
t susp
30
DS582F2
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