CS4341A(2002) 查看數據表（PDF） - Cirrus Logic
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CS4341A Datasheet PDF : 32 Pages
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CS4341A
5. REGISTER DESCRIPTION
NOTE: All registers are read/write in I2C mode and write only in SPI mode, unless otherwise stated.
5.1 MODE CONTROL 1 (ADDRESS 00H)
7
Reserved
0
6
MC1
0
5
MC0
0
4
Reserved
0
3
Reserved
0
2
AUTOD
0
1
MCLKDIV
0
0
Reserved
0
5.1.1 SPEED MODE CONTROL (MC) BIT 5-6
Default = 00
00 - Single-Speed Mode
01 - Double-Speed Mode
10 - Quad-Speed Mode
The operational speed mode must be set if the auto-detect defeat bit is enabled (AUTOD = 1). These
bits are ignored if the auto-detect defeat is disabled (AUTOD = 0).
5.1.2 AUTO-DETECT DEFEAT (AUTOD) BIT 2
Default = 0
0 - Disabled
1 - Enabled
The Auto-Detect function can be defeated to allow sample rate changes from 50 to 84 kHz, and from
100 to 170 kHz. The operational speed mode must be set via the speed mode control bits (see section
5.1.1) if the auto-detect feature is defeated.
5.1.3 MCLK DIVIDE-BY-2 (MCLKDIV) BIT 1
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.
5.2 MODE CONTROL 2 (ADDRESS 01H)
7
AMUTE
1
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
DEM1
0
2
DEM0
0
1
POR
1
0
PDN
1
DS582PP1
15
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