CS5322-BL(2005) 查看數據表（PDF） - Cirrus Logic

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CS5322-BL
(Rev.:2005)

24-bit, Variable-bandwidth A/D Converter Chipset

Cirrus Logic 

CS5321/22

2.4 Voltage Reference

The CS5321 is designed to operate with a voltage

reference in the range of 4.0 to 4.5 Volts. The volt-

age reference is applied to the VREF+ pin with the

VREF- pin connected to the GND. A 4.5 V refer-

ence will result in the best S/N performance but

most 4.5 V references require a power supply volt-

age greater than 5.0 V for operation. A 4.0 V refer-

ence can be used for those applications which must

operate from only 5.0 V supplies, but will yield a

S/N slightly lower (1-2 dB) than when using a 4.5

V reference. The voltage reference should be de-

signed to yield less than 2 µVrms of noise in band

at the VREF+ pin of the CS5321. The CS5322 filter

selection will determine the bandwidth over which

the voltage reference noise will affect the

CS5321/22 dynamic range.

For a 4.5 V reference, the LT1019-4.5 voltage ref-

erence yields low enough noise if the output is fil-

tered with a low pass RC filter as shown in Figure

21 Option A. The filter in Figure 21 Option A is ac-

ceptable for most spectral measurement applica-

tions, but a buffered version with lower source

impedance (Figure 21 Option B) may be preferred

for dc-measurement applications. Due to its dy-

namic (switched-capacitor) input the input imped-

ance of the +VREF pin of the CS5321 will change

any time MCLK or HBR is changed. Therefore the

current required from the voltage reference will

change any time MCLK or HBR is changed. This

can affect gain accuracy due to the high source im-

pedance of the filter resistor in Figure 20 and Fig-

ure 21 Option A. If gain error is to be minimized,

especially when MCLK or HBR is changed, the

voltage reference should have lower output imped-

ance. The buffer of Figure 21 Option B offers lower

output impedance and will exhibit better system

gain stability.

2.5 Clock Source

For proper operation, the CS5321 must be provided

with a CMOS-compatible clock on the MCLK pin.

The MCLK for the CS5321 is usually provided by

the CS5322 filter. MCLK is usually 1.024 MHz to

set the seven selectable output word rates from the

CS5322. The MCLK frequency can be as low as

250 kHz and as high as 1.2 MHz. The choice of

clock frequency can affect performance; see the

Performance section of the data sheet. The clock

+9 to

15V

10 Ω

0.1 µF

L T 1 0 1 9 -4 .5

Option A

200 Ω

0.1 µF

+ 68 µF

To VREF+

Option B

1k Ω

+

10k Ω

+

49.9 Ω

100 µF

AL

100 µF

AL

+9 to 15V

+

100 Ω

-

1k Ω

LT1007

0.1 µF

+ 68 µF

Tant

To VREF+

Figure 21. 4.5 Voltage Reference with two filter options

20

DS454F2

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