AAT3218IJS-1.5-T1 查看數據表（PDF） - Analog Technology Inc
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AAT3218IJS-1.5-T1 Datasheet PDF : 18 Pages
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AAT3218
150mA MicroPower™ High Performance LDO
Applications Information
VIN
IIN
DC INPUT
VIN
LDO
VOUT
Regulator
EN
BYP
GND
CIN
IRIPPLE
IGND
IBYP + noise
ILOAD
CBYP
GND
LOOP
CBYP
COUT
RLOAD
GND
RTRACE
RTRACE
RTRACE
RTRACE
ILOAD return + noise and ripple
Figure 1: Common LDO Regulator Layout with CBYP Ripple feedback loop
Figure 2 shows the preferred method for the bypass
and output capacitor connections. For low output
noise and highest possible power supply ripple
rejection performance, it is critical to connect the
bypass and output capacitor directly to the LDO reg-
ulator ground pin. This method will eliminate any
load noise or ripple current feedback through the
LDO regulator.
IIN
VIN
DC INPUT
ILOAD
VIN
LDO
VOUT
Regulator
EN
BYP
GND
CIN
IRIPPLE
IGND
IBYP only
CBYP
GND
RTRACE
RTRACE
ILOAD return + noise and ripple
RTRACE
Figure 2: Recommended LDO Regulator Layout
COUT
RTRACE
RLOAD
Evaluation Board Layout
The AAT3218 evaluation layout follows the recom-
mend printed circuit board layout procedures and
can be used as an example for good application
layouts.
Note: Board layout shown is not to scale.
Figure 3: Evaluation board
component side layout
14
Figure 4: Evaluation board
solder side layout
Figure 5: Evaluation board
top side silk screen layout /
assembly drawing
3218.2004.02.1.0
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