AAT1112
1.5A, 1.4MHz Step-Down Converter
Layout
The suggested PCB layout for the AAT1112 is
shown in Figures 2 and 3. The following guidelines
should be used to help ensure a proper layout.
1. The input capacitor (C1) should connect as close-
ly as possible to VP and PGND.
2. C2 and L1 should be connected as closely as
possible. The connection of L1 to the LX pin
should be as short as possible.
3. The feedback trace or FB pin should be sepa-
rate from any power trace and connect as
closely as possible to the load point. Sensing
along a high-current load trace will degrade DC
load regulation.
4. The resistance of the trace from the load return
to PGND should be kept to a minimum. This
will help to minimize any error in DC regulation
due to differences in the potential of the inter-
nal signal ground and the power ground.
5. Connect unused signal pins to ground to avoid
unwanted noise coupling.
SYNC
Vin
LL PWM
GND
GND
L1 C1
On
LX
Vout
Off
U1
R3 Enable
C3
C2 R2
GND
AAT1112
AnalogicTech
Figure 2: AAT1112 Evaluation Board
Top Side Layout.
SYNC
C4
Vin
LL PWM
GND
GND
L1 C1
On
LX
Vout
Off
U1
R3 Enable
C3
C2 R2
GND
AAT1112
AnalogicTech
Figure 3: AAT1112 Evaluation Board
Bottom Side Layout.
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