
STM32F405xx, STM32F407xx
Electrical characteristics
High
NSS input
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
Figure 42. SPI timing diagram - master mode
tc(SCK)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO
INP UT
tsu(MI)
MOSI
OUTU T
tw(SCKH)
tw(SCKL)
MS BIN
th(MI)
M SB OUT
tv(MO)
BI T6 IN
B I T1 OUT
th(MO)
tr(SCK)
tf(SCK)
LSB IN
LSB OUT
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