CS4398CZZ 查看數據表（PDF） - Cirrus Logic

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CS4398CZZ

120 dB, 192 kHz Multi-Bit DAC with Volume Control

Cirrus Logic 

CS4398

CS

CCLK

CDIN

CHIP

ADDRESS

1001100

MAP

DATA

R/W

MSB

LSB

byte 1

MAP = Memory Address Pointer

byte n

Figure 15. Control Port Timing, SPI Format (Write)

5.5.2

Reading in SPI

Figure 16 shows the operation of the Control Port in SPI format. To read to a register, bring CS low. The

first seven bits on CDIN form the chip address and must be 1001100. The eighth bit is a read/write control

(R/W), which must be high to read. The CDOUT line will then output the data from the register designated

by the MAP. To read multiple registers, keep CS low and continue providing clocks on CCLK. End the

read transaction by setting CS high. The CDOUT line will go to a high-impedance state once CS goes

high.

CS

CCLK

C D IN

CDOUT

C H IP

ADDRESS

1001100

R /W

MSB

DATA

LSB

byte 1

byte n

Figure 16. Control Port Timing, SPI Format (Read)

DS568F1

27

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