SI3014-KS 查看數據表（PDF） - Silicon Laboratories
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SI3014-KS Datasheet PDF : 64 Pages
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Si3038
Register 40h Line 1 DAC/ADC Rate
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
Reset settings = 0x0000
Each DAC/ADC pair is governed by a read/write modem sample rate control register that contains a 16-bit
unsigned value between 0 and 65535, representing the rate of operation in Hz. A number written over 0x3592 will
cause the sample rate to be 13.714 kHz. For all rates, if the value written to the register is supported, that value will
be echoed back when read, otherwise the closest rate supported is returned.
When set to zero, the internal PLL is disabled. The PLL should be programmed before the line side (Si3014) is
activated via clearing any PR bit in register 3Eh. Furthermore, sleep mode is not supported when the PLL is
disabled.
Sample rates for Line 1 and
Line 2
Sample Rate
D15–D0
7200
1C20
8000
1F40
8228.57 (57600/7) 2024
8400
20D0
9000
2328
9600
2580
10285.71 (72000/7) 282D
12000
2EE0
13714.28 (96000/7) 3592
Register 42h Line 2 DAC/ADC Rate
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
Reset settings = 0x0000 (rates same as for Line 1, refer to above table)
Rev. 2.01
41
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