3851 Group (Built-in 24 KB or more ROM)
Table 8 Interrupt vector addresses and priority
Interrupt Source Priority
Vector Addresses (Note 1)
High
Low
Reset (Note 2)
1
FFFD16
FFFC16
INT0
2
FFFB16
FFFA16
SCL, SDA
3
FFF916
FFF816
INT1
4
FFF716
FFF616
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of SCL or SDA input
At detection of either rising or
falling edge of INT1 input
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
INT2
5
FFF516
FFF416
At detection of either rising or External interrupt
falling edge of INT2 input
(active edge selectable)
INT3
Serial I/O2
6
I2C
7
Timer X
8
Timer Y
9
Timer 1
10
Timer 2
11
Serial I/O1
reception
12
Serial I/O1
transmission
13
CNTR0
14
CNTR1
15
A-D converter
16
BRK instruction
17
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
At detection of either rising or
falling edge of INT3 input
At completion of serial I/O2 data
reception/transmission
External interrupt
(active edge selectable)
Switch by Serial I/O2/INT3
interrupt source bit
At completion of data transfer
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At completion of serial I/O1 data
reception
STP release timer underflow
Valid when serial I/O is selected
At completion of serial I/O1
transfer shift or when transmis-
sion buffer is empty
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At completion of A-D conversion
At BRK instruction execution
Valid when serial I/O is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Rev.1.01 Oct 15, 2003 page 18 of 89