Z80230 查看數據表（PDF） - Zilog

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Z80230

Zilog SCC Serial Communication Controller

Zilog 

Application Note

Boost Your System Performance Using The Zilog ESCC™

RECEIVE FIFO INTERRUPT

In the ESCC, receive interrupt frequencies are reduced

due to a deeper Receive FIFO and the revised receive

interrupt structure.

If WR7' D3 Receive FIFO Interrupt Level bit is reset, the

ESCC generates the receive character available interrupt

on every received character. This is compatible with SCC

Receive Character Available Interrupt. If WR7' D3 is set,

the Receive Character Available Interrupt is triggered

when the Receive FIFO is half full; the first four locations

from the entry are still empty. By enabling the receive FIFO

interrupt level, together with polling the Receive Character

Available (RCA) bit in RR0, the receive interrupt

frequencies are reduced significantly. Receive data is read

in blocks of four bytes (Figure 5). This would help to offload

systems which have a long interrupt latency and heavily

loaded Operating Systems.

RX FIFO Int.

Level Enabled

RCA Interrupt

Service

NO

RX FIFO

Empty

RR0

RCA = '1'?

YES

Read Data

From RX FIFO

All Data in

RX FIFO Have

Been Read

Figure 5. Flowchart of Receive Interrupt Service Routine to Reduce Receive Interrupt Frequencies

6-122

UM010901-0601

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