PSD913G3V-C-20B81I 查看數據表（PDF） - STMicroelectronics

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PSD913G3V-C-20B81I

Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs

STMicroelectronics 

Preliminary Information

PSD9XX Family

Microcontroller Interface – PSD9XXFV AC/DC Parameters

(3 V Versions)

Power Down Timing (3 V Versions)

-12

-15

-20

Symbol

Parameter

Conditions Min Max Min Max Min Max Unit

t LVDV

ALE Access Time from

Power Down

t CLWH

Maximum Delay from APD Enable

to Internal PDN Valid Signal

NOTE: 1. tCLCL is the CLKIN clock period.

Using

CLKIN Input

145

150

200 ns

15 * tCLCL (µs) (Note 1)

µs

Vstbyon Timing (3 V Versions)

Symbol

Parameter

t BVBH

Vstby Detection to Vstbyon Output

High

t BXBL

Vstby Off Detection to Vstbyon

Output Low

NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms.

Conditions

(Note 1)

(Note 1)

Min

Typ

Max Unit

20

µs

20

µs

Reset Pin Timing (3 V Versions)

Symbol

Parameter

t NLNH

t OPR

t NLNH-PO

t NLNH-A

Warm RESET Active Low Time (Note 1)

RESET High to Operational Device

Power On Reset Active Low Time

Warm Reset, will abort and reset Flash

programming/erase cycles to Read

mode. For PSD9X4FV only.

NOTE: 1. RESET will not reset Flash programming/erase cycles.

2. RESET will abort Flash programming or erase cycle.

Conditions

Min

Typ

Max Unit

300

ns

300

ns

1

ms

25

µs

75

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