PSD913G3V-C-90UI 查看數據表（PDF） - STMicroelectronics
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PSD913G3V-C-90UI Datasheet PDF : 94 Pages
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PSD9XX Family
Preliminary Information
PSD9XXFV DC Characteristics (3.0 V to 3.6 V Versions) Advance Information
Symbol
Parameter
Conditions
Min Typ Max Unit
VCC
VIH
VIL
VIH1
VIL1
VHYS
VLKO
VOL
VOH
VOH1
VSBY
ISBY
IIDLE
VDF
ISB
ILI
ILO
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Reset High Level Input Voltage
Reset Low Level Input Voltage
Reset Pin Hysteresis
VCC Min for Flash Erase and Program
Output Low Voltage
Output High Voltage Except VSTBY On
Output High Voltage VSTBY On
SRAM Standby Voltage
SRAM Standby Current (VSTBY Pin)
Idle Current (VSTBY Pin)
SRAM Data Retention Voltage
Standby Supply Current
for Power Down Mode
Input Leakage Current
Output Leakage Current
ICC (DC) Operating
(Note 5) Supply Current
PLD Only
FLASH
All Speeds
3.0
3.0 V < VCC < 3.6 V
3.0 V < VCC < 3.6 V
(Note 1)
(Note 1)
.7 VCC
– .5
.8 VCC
–.5
0.3
1.5
IOL = 20 µA, VCC = 3.0 V
IOL = 4 mA, VCC = 3.0 V
IOH = –20 µA, VCC = 3.0 V
2.9
IOH = –1 mA, VCC = 3.0 V
IOH1 = –1 µA
2.7
VSBY – 0.8
2.0
VCC = 0 V
VCC > VSBY
Only on VSTBY
– 0.1
2
CSI >VCC –0.3 V
(Notes 2 and 3)
VSS < VIN < VCC
–1
0.45 < VIN < VCC
–10
PLD_TURBO = OFF,
f = 0 MHz (Note 3)
PLD_TURBO = ON,
f = 0 MHz
During FLASH or
Write/Erase Only
0.01
0.15
2.99
2.8
0.5
25
±.1
±5
0
200
10
3.6
VCC +.5
0.8
VCC +.5
.2 VCC –.1
2.2
0.1
0.45
VCC
1
0.1
100
1
10
400
25
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
V
µA
µA
µA
mA
µA/PT
mA
Read Only, f = 0 MHz
0
0
mA
SRAM
f = 0 MHz
0
0
mA
PLD AC Adder
(Note 4)
Figure26a
ICC (AC) FLASH
(Note 5) AC Adder
1.5
2.0 mA/MHz
SRAM AC Adder
0.8
1.5 mA/MHz
NOTES: 1.
2.
3.
4.
5.
Reset input has hysteresis. VIL1 is valid at or below .2VCC –.1. VIH1 is valid at or above .8VCC.
CSI deselected or internal PD is active.
PLD is in non-turbo mode and none of the inputs are switching.
Refer to Figure 26a for PLD current calculation.
IOUT = 0 mA.
72
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