PSD913G3V-C-90MI 查看數據表（PDF） - STMicroelectronics
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PSD913G3V-C-90MI Datasheet PDF : 94 Pages
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Preliminary Information
PSD9XX Family
Microcontroller Interface – PSD9XX AC/DC Parameters
(5V ± 10% Versions)
Write Timing (5 V ± 10% Versions)
-70
-90
-15
Symbol
Parameter
Conditions
Min Max Min Max Min Max Unit
t LVLX
t AVLX
t LXAX
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
15
20
28
(Note 1)
4
6
10
ns
(Note 1)
7
8
11
ns
t AVWL
Address Valid to Leading Edge of WR
(Notes 1 and 3)
8
15
20
ns
t SLWL
CS Valid to Leading Edge of WR
(Note 3)
12
15
20
ns
t DVWH WR Data Setup Time
(Note 3)
25
35
45
ns
t WHDX
t WLWH
WR Data Hold Time
WR Pulse Width
(Note 3)
4
5
5
ns
(Note 3)
31
35
45
ns
tWHAX1 Trailing Edge of WR to Address Invalid
(Note 3)
6
8
10
ns
t WHAX2
Trailing Edge of WR to DPLD Address
Input Invalid
(Note 3 and 4)
0
0
0
ns
t WHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
27
30
38 ns
t AVPV
Address Input Valid to Address
Output Delay
(Note 2)
20
25
30 ns
NOTES: 1.
2.
3.
4.
Any input used to select an internal PSD9XX function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
PLD Combinatorial Timing (5 V ± 10%)
Symbol
t PD
t ARD
Parameter
PLD Input Pin/Feedback
to PLD Combinatorial
Output
PLD Array Delay
-70
-90
-15
Fast
Slew
PT TURBO Rate
Conditions Min Max Min Max Min Max Aloc OFF (Note 1) Unit
20
25
32 Add 2 Add 10 Sub 2 ns
Any
11
Micro⇔Cell
16
22 Add 2
ns
NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
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